1. Field of the Invention
The invention relates in general to a radar scan converter (RSC). More particularly, to a radar scan converter and a method of directly overlaying a video on a screen of a personal computer without deteriorating the original graphic.
2. Description of the Related Art
The conventional radar display is a cylindrical cathode ray tube (CRT). A CRT screen has a beam spinning synchronously with the antenna. A target is displayed on the beam and vanishes automatically after a while. This kind of display apparatus is called plan position indicator (PPI). Since PPI achieves the objective of a delay of target vanishment based on the persistence of a phosphor, the brightness is often low to demand a dim environment. Moreover, the cost of this kind of CRT is high.
To overcome the problems of PPI, various kinds of digital scan converters (DSC) have been developed. DSC converts the radius and angle of the beam into corresponding X- and Y-coordinates of a TV monitor. In addition, being referenced by a recording technique of computer video, for example, multi-color display, overlaying window, and adding text onto the display, the radar display is integrated.
FIG. 1 is a block diagram showing function of a conventional digital scan converter. The digital scan converter 10 comprises an analog-to-digital (A/D) converter 12, a radial buffer 14, a decimation filter 16, a control unit 18, a coordinate converter 20, a frame buffer 22, a memory/display timing generator 24 and a digital-to-analog (D/A) converter 26. Being digitized by the A/D converter 12, a radar video is stored in the radial buffer 14. The data stored in the radial buffer 14 are then processed by the decimation filter 16 according to a predetermined display range.
An azimuth information of radar, the AZ synchronous signal (AZ sync), comprises an azimuth reference pulse (ARP) and an azimuth change pulse (ACP). When the antenna is spinning, there are 4096 ACP and 1 ARP per revolution. The ARP appears while the antenna spins towards the true north direction. A trigger signal (Trigger) indicates the moment while radar wave is emitted, that is, Trigger coincident with range zero. According to the AZ sync, the coordinate converter 20 calculates a coordinate (R,.THETA.) in a polar coordinate system and converts it into a coordinate (X,Y) in a Cartesian coordinate system.
Using the coordinate (X,Y) in the Cartesian coordinate system as an address, the memory/display timing generator 24 stores the data being processed by the decimation filter 16 into the frame buffer 22. In addition, the memory/display timing generator 24 undertakes access of the data stored in the frame buffer 22 and generation of a TV synchronous signal (TV sync). The output of the frame buffer 22 is a digital signal. The D/A converter 26 converts this digital signal into an analog signal which is then sent to a TV monitor together with the TV sync. Similar structures of the DSC have been disclosed in U.S. Pat. Nos. 4,754,279, 4,729,029, 4,675,679, 4,434,422, 4,412,220, 4,220,969, 4,065,770 and 4,002,827.
The coordinate converter 20 is one of the characteristics of DSC. Conventionally, the polar coordinate (R,.THETA.) can be converted into the Cartesian coordinate (X,Y) with multipliers and Look Up table established by sine and cosine functions. In U.S. Pat. No. 4,729,029, an adders are used to simplify and speed up the conversion. The following patents such as U.S. Pat. Nos. 4,697,185, 4,931,801, 5,519,401, 5,530,450 and 5,554,992 further discloses methods to overcome the problems of overwriting and spoking.
In addition, the frame buffer 22 is a key module for signal flow. Since the structure of memory directly affects the process speed of signal, resolving methods have been disclosed in U.S. Pat. Nos. 4,220,969, 4,065,770 and 4,002,827.
As the technique of electronic device becomes more and more advanced, the computer becomes more and more powerful. With the disclosure of VME bus, a combination of a DSC and a computer workstation becomes a trend. FIG. 2 shows a functional block diagram of a radar scan converter comprising an analog multiplexer (MUX).
Similar to FIG. 1, U.S. Pat. No. 5,418,535 discloses a method of forming a DSC into a VME bus, wherein the DSC is incorporated with an overlay function which can mix the images of the radar video and the workstation and send the mixed image to the monitor. The method of overlay comprises combining of the video of D/A converter output and the graphics of workstation 32 to a multiplexer 34, and determining the switching of the multiplexer 34 according to the voltage level of the graphics. The technique terminology of "RSC" is commonly used in this stage of development.
In the current chapter of multi-media computer, many patents have disclosed methods of overlaying video of TV camera and computer graphic. A multiplexer is used to perform the overlay. In Taiwanese Patent No. 264,548, U.S. Pat. Nos. 5,398,075 and 5,220,312, analog image overlay is adopted, while Taiwanese Patent No. 286,381 and U.S. Pat. No. 5,598,525 belong to a digital image overlay since a digital multiplexer is in use.
The analog multiplexer which adopts a current summing approach comprises a high speed switch device. Since the high speed switch device has a nonlinear impedance, distortion is resulted in the image. In addition, the low-pass filtering effect of limited bandwidth components results in the blurring and smearing of image. For a screen with a resolution of 1280.times.1024 and a vertical frequency of 60 Hz, the pixel frequency is 108 MHz. It is known that a switch delay of 10 ns would cause the image to shift with one pixel position. Therefore, the switch frequency of the multiplexer is required as high as 100 MHz. To avoid distortion and noise, the bandwidth and linearity have to be enhanced. This further increases the circuit complexity and the fabrication cost.
Based on the problems as described above, a digital multiplexer is used instead of an analog one. FIG. 3 shows a functional block diagram of a conventional radar scan converter comprising a digital multiplexer. A D/A converter 40 is disposed behind a digital multiplexer 42, and a color key comparator 44 determine the switching of the digital multiplexer 42 according to color bits of graphic, for example, 8, 15, 16 or 24 bits.
In FIG. 3, a digital graphic is sent from the workstation 46 to the RSC 48 via a feature connector (not shown). The frequency of the feature connector is limited at 45 MHz. However, the transmission of an analog signal between the workstation 46 and the RSC 48 can reach as high as 135 MHz.
There is another problem of the above feature connector. In response with video graphics array (VGA) card with different brand name, the transmission format of the digital graphic may be 8, 15, 16 or 24 bits, and the settling time and holding time of pixel clock of various VGA card are different. To moderate the problem of incompatibility, the pixel clock and digital graphic has to be re-buffered and regenerated. This increase the cost and complexity of RSC card further.
From the above introduction, the conventional RSC comprises a frame buffer, a multiplexer, a color key comparator and a D/A converter. The relative circuit of the frame buffer comprises random access memory (RAM), address register, read/write controller and timing generator. The memory structure affects the path and speed of signal processing, and hence, the circuit is complex.